The present invention relates to electronic memories and more particularly to a random access memory (RAM), designed for use in a digital signal processor, which has a unique structure permitting simplified addressing for movement of data.
A digital signal processor is a high speed microcomputer capable of performing a variety of specialized functions requiring digitally adaptive, secure and intelligent signal processing. Examples of such applications are pattern recognition, adaptive control storage, intelligent finite impulse response filtering, linear circuit control, encryption algorithm execution, diagnostics, precision servo control and voice band data processing. Such processors find use in industrial robots, modems and direct broadcast satellite signal encryption systems.
One example of a digital signal processor which is currently commercially available is manufactured and distributed by the Microchip division of General Instrument Corporation at 767 Fifth Avenue, New York, N.Y. and designated as DSP 320C10. This processor has separate program and data memories which permit coefficients stored in the program memory to be read into the data memory, eliminating the need for a separate coefficient read only memory. A barrel shifter shifts data through the processor which includes an arithmetic logic unit and an accumulator. A multiplier is included which can perform a multiplication in a single 160 ns cycle. Auxiliary registers provide indirect data RAM addresses. Special hardware is employed so that the registers can be configured in an autoincrement/decrement mode for single-cycle manipulation of data tables.
This processor is equipped with a 1536 word mask programmable read only memory (ROM). It can also execute instructions from an additional 2560 words of off chip memory, at full speed. A 144 word data RAM is provided.
The present invention relates to an improved digital signal processor which employs the same basic architecture as the DSP320C10 but includes 2.5K words of electronically erasable programmable read only memory (EEPROM) instead of the 1.5K words of mask programmable ROM and a larger RAM, 256 words as compared to 144. In particular, it relates to one of several improvements in the processor directed at providing enhanced operating characteristics through expansion of the RAM structure.
Certain processing applications require repeated moving of data from one designated memory location to another. For example, in implementing certain algorithms in finite impulse response filters, values for different time slots are sampled and stored in memory as the weighted sum thereof is calculated. Each value is shifted to a new location in the memory, preferably the next memory location in sequence, after each time slot. Thus, a new value for the current slot is added at the beginning of the memory chain as the oldest value is deleted from the end of the memory chain. The weighted sum is then calculated and stored. Hence, at the end of each time slot, the data at each memory location must be transferred to a different (next) memory location and the weighted sum calculated. This data movement requires the execution of a read command, relative to a first designated memory address, and then the execution of a write command, relative to a second designated memory address.
In the commercially available GI digital signal processor, a single continuous RAM decoder circuit was used for this purpose. During the first half of the time cycle, a first address is decoded, located and the data therein is read. At the same time, the second address is calculated. During the second half of the time cycle, the second address is decoded, located and the data written therein. This is a straightforward way of handling the shifting problem.